The present invention relates to digital logic circuits and more particularly to a flip-flop circuit.
All digital systems use timing devices such as latches and flip-flops as part of the digital system. As the operating frequencies increase and the number of logic gates between timing elements are reduced, timing constraints are reflected on the design of flip-flops. Additionally, low delay from the clock input to data output, shorter setup and hold times are required. Other critical elements of high-speed flip-flop design are low-power operation, small size and low clock load.
Many digital systems, require incorporation of asynchronous set and reset in these flip-flops. This requirement is common in communications and digital signal processing applications, such as modems, or disk-drive read channels.
The prior art has presented many flip-flop structures. One such flip-flop structure is illustrated in FIG. 1. This flip-flop has a first stage 102 and a second stage 104. The second stage 104 includes an R-S latch. The first stage 102 of this flip-flop includes a sense amplifier which is widely used in memory integrated circuits. Differential inputs D and {overscore (D)} of the first stage 102 sense the difference between the inputs. The inputs to the first stage 102 can be obtained from either a dual or single-rail logic. With single-rail logic, a complementary output can be generated by use of an inverter. This sense amplifier stage produces monotonous transitions from the high to low logic levels at nodes {overscore (S)} and {overscore (R)} on the leading clock edge, and the S-R latch captures each monotonous transition and holds the state until the next leading clock edge arrives. Thus, the whole structure operates as a flip-flop.
The S-R latch operates such that the input {overscore (S)} is a set input and {overscore (R)} is a reset input. The low level at both {overscore (S)} and {overscore (R)} inputs are not simultaneously permitted, and this low level at both {overscore (S)} and {overscore (R)} is prevented by the sense-amplifier stage 102. The low level at {overscore (S)} sets the Q output to high, which in turn forces the {overscore (Q)} to low. Conversely, the low level at {overscore (R)} sets the {overscore (Q)} to high, which in turn forces Q to low. Thus, one of the outputs is always delayed with respect to the other.
Sense amplifier-based flip-flops achieve very small delay between the latest point of data arrival (consisting of the sum of setup time and clock-to-output delay), but integration of asynchronous set and reset functions has not been accomplished.
The sense-amplifier flip-flop of the present invention provides asynchronous set and reset functions.
The present invention allows the first stage of the sense amplifier based flip-flop to incorporate the asynchronous set and reset. Since the sense amplifier flip-flop is pulse triggered, the asynchronous set and reset features should be incorporated in the first stage for proper setting and resetting as well as for the recovery to normal mode of operation.
Incorporation of asynchronous set and reset into the sense amplifier-based flip-flop has small impact on the speed, and does not adversely affect other properties. The output stage from FIG. 2 has the same delays of both true Q and complementary outputs {overscore (Q)} and the same delays for both falling and rising edges.
Asynchronous set and reset signals are implemented in the first stage, and these set and reset signals change the outputs via {overscore (S)} and {overscore (R)} signals.
Additionally, the transitions of the output signals Q and {overscore (Q)} depend only on transitions of signals {overscore (S)} and {overscore (R)}.
When the clock signal is low, in normal operation, nodes {overscore (S)} and {overscore (R)} are precharged through two transistors. This precharging is gated by two other transistors for the asynchronous set and reset insertion. If flip-flop is in the set or reset state, {overscore (S)} and {overscore (R)} nodes are not precharged.
In normal operation, the high states of {overscore (S)} and {overscore (R)} keeps a pair of transistors on, charging their sources to a predetermined voltage since there is no path to ground due to the clocked off state of an additional transistor. The sense-amplifier stage is triggered on the leading edge of the clock. If the signal D is high, node {overscore (S)} is discharged through a first path. If {overscore (D)} is high, node {overscore (R)} is discharged through a second path. After this change, additional changes of the data inputs will not affect the state of {overscore (S)} and {overscore (R)} nodes. The inputs are decoupled from the outputs of the sense amplifier and thus form the basis for the flip-flop operation of the circuit.
The transitions generated by the sense amplifier are captured in the S-R latch to produce a new flip-flop state.
The present invention provides the integration of the asynchronous set and reset functions into the flip-flop with small impact on the performance.